Timing method and apparatus for interleaving PIO and DMA data transfers

摘要

The present invention is directed at prioritizing and interleaving data transfer protocols between storage mediums and main memories. The invention includes a controller interface that is operatively connected to a plurality of storage mediums, a main memory and a central processing unit (CPU). The controller interface is preferably configured to receive and detect data transfer protocol requests having different timing parameters. Once the controller interface receives a data transfer protocol request, an arbitration unit that is operatively coupled to said controller interface assigns priorities to the detected data transfer protocols having different timing parameters. The arbitration unit then compares the assigned priorities, and interrupts an on-going data transfer protocol when a newly received data transfer protocol is assigned a higher priority. The data transfer protocol assigned the high priority is then commenced and proceeds to completion. Once the high priority data transfer protocol is complete, the interrupted data transfer protocols may be resumed.