发明名称 |
Methods for fabricating anti-fuse structures |
摘要 |
A method for substantially reducing variations in a programming voltage of an anti-fuse structure formed on an integrated circuit wafer. The anti-fuse structure has a metal-one layer, an anti-fuse layer disposed above the metal-one layer, a oxide layer disposed above the anti-fuse layer, and a via hole in the oxide layer through to the anti-fuse layer for receiving a deposition of a metal-two material. The method includes the step of rendering a selected anti-fuse area susceptible to fuse link formation by reducing a resistivity of the selected anti-fuse area to diffusion of atoms from one of the metal-one layer and the metal-two layer when a programming voltage is applied between the metal one layer and the metal two layer. The selected anti-fuse area is located in the anti-fuse layer and substantially adjacent to and outside of an anti-fuse area directly below the via hole. The method further includes the step of depositing the metal-two material into the via hole.
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申请公布号 |
US5793094(A) |
申请公布日期 |
1998.08.11 |
申请号 |
US19950579780 |
申请日期 |
1995.12.28 |
申请人 |
VLSI TECHNOLOGY, INC. |
发明人 |
SANCHEZ, IVAN;HAN, YU-PIN;LOH, YING-TSONG;PARMANTIE, WALTER D. |
分类号 |
H01L23/525;(IPC1-7):H01L29/00 |
主分类号 |
H01L23/525 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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