| 摘要 |
PROBLEM TO BE SOLVED: To reduce a step between a cell array part and a periphery circuit part, by providing an interface part between the cell array part and the periphery circuit part with a dummy line of word line and bit line. SOLUTION: A gate insulation film 45, a polysilicon layer 46, and a cap oxide layer 47 formed on a cell array part are selectively patterned to form a work line of memory element, and such gate insulation film, polysilicon layer, and cap oxide film as formed at a periphery circuit part are selectively patterned, so that a gate line of transistor constituting a periphery circuit part is formed. Here, patterning is so performed that one or more dummy word lines may remain at the part, of an isolation layer where not word line is formed. Further, on an insulation layer on the isolation layer where a dummy word line comprising a polysilicon layer, etc., patterning is so performed that a dummy bit line comprising a polysilicon layer and a tungsten silicide layer may remain. |
