| 摘要 |
A semiconductor integrated circuit in which high-speed data transfer is possible and reloading of data is unnecessary when the contents of the data memory are the same as the previous contents. The timing for starting the sampling of the number of driver chips cascade connected with an output terminal and input terminal ST is provided by flip-flop 103, which is the internal counter, and only propriety for starting is executed with respect to a cascade connection, namely, input terminal ST in the next step from output terminal OUT. Therefore, the timing for transmitting a cascade signal is determined by flip-flops 103 and 104, which are the 2-bit internal counters. For example, in the case of a 2-bit counter, all that is necessary is for the cascade signal to be transmitted for two cycles so the overall transfer speed is not restricted in this part and high-speed data transfer becomes possible.
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