| 摘要 |
An apparatus uses parasitic capacitances between each of one or more leads and a spaced apart electrically conductive plane on a Printed Circuit Board (PCB) to store data transmitted on the one or more leads until new data is transmitted over the one or more leads from first or second devices interconnected by the one or more leads. The first device is responsive to a first control signal for modifying the data on the one or more leads and transmitting the modified data back onto the one or more leads. Alternatively, the first device is responsive to a second control signal for inhibiting the first device from reading the data from the one or more leads and from transmitting any data back onto the one or more leads for at least one clock cycle. When the first device is responsive to the second control signal, the data stored in the parasitic capacitances are, for example, read back into the second device and/or used as an output of the apparatus during a predetermined time period.
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