发明名称 BURST CLOCK CORRESPONDING MEMORY CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a burst clock corresponding memory circuit using a burst clock signal in which correspondence to an arbitrary transmitting speed and the quality security of a stable transmission signal can be attained in transmission between the communication equipments of an opposite station and its own station. SOLUTION: In this communication system, the constitutions of an opposite station and its own station as communication equipments are made the same, and this system is provided with a burst clock corresponding memory circuit using a burst clock signal as a clock signal for writing in a memory to be used for transmission between the communication equipments. In the burst clock corresponding memory circuit, a clock generating circuit 4 generates a reading clock signal at a transmitting speed obtained by averaging the burst clock signal which is synchronizing with it in response to a reading permission signal from a first memory 3, and a second memory 5 uses the reading clock signal as a clock signal for writing, and successively writes a transmission signal S read from the first memory 3.</p>
申请公布号 JPH10207761(A) 申请公布日期 1998.08.07
申请号 JP19970012529 申请日期 1997.01.27
申请人 NEC CORP 发明人 SONODA YUKIO
分类号 G06F12/00;G06F5/06;G06F13/00;G06F13/42;G11C7/00;G11C7/22;H04L7/00;(IPC1-7):G06F12/00 主分类号 G06F12/00
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