发明名称 |
VOLTAGE LIMIT CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND IC CARD |
摘要 |
PROBLEM TO BE SOLVED: To realize a data reception circuit (input circuit), for which power consumption and a power loss are less and by which a high frequency input signal is given to an internal circuit, while its voltage is limited with respect to a transceiver use semiconductor integrated circuit mounted on a contactless IC card employing electromagnetic coupling. SOLUTION: A diode D1 is connected between an emitter of a bipolar transistor(TR) Q1, whose base receives a constant voltage and a terminal T1(T2) receiving an AC signal, so as to prevent a current flowing from the input terminal when the input signal increases more than a prescribed level. Moreover, a level of the signal delivered to an internal circuit for that time is clamped by a base-emitter junction of the bipolar TR Q1. |
申请公布号 |
JPH10209782(A) |
申请公布日期 |
1998.08.07 |
申请号 |
JP19970006164 |
申请日期 |
1997.01.17 |
申请人 |
HITACHI LTD;HITACHI CHIYOU LSI SYST:KK |
发明人 |
KADOKAWA SHIGERU;TSUNODA HISATAKA;ANDO MASAAKI |
分类号 |
G06K19/07;H03G11/00;H04B5/02 |
主分类号 |
G06K19/07 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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