| 摘要 |
PROBLEM TO BE SOLVED: To provide the pulse signal generator with a simple configuration that generates a pulse width modulation(PWM) signal consisting of an open loop having a uniform clock system. SOLUTION: A PWM voltage generator includes a PLL that generates a clock square wave signal whose frequency is twice a desired resolution frequency of a PWM output signal. A PWM controller 14 receives the clock square wave signal and a data signal and provides an output of a PWM signal with a duty cycle depending on the data signal with the frequency of the clock square wave signal. A switching circuit coupled with the PWM controller 14 receives a signal from a frequency divider 16 being a component of the PLL and switches the output of the generator so as to be floated for a first half of the PWM frame cycle so that the PWM output signal includes no PWM output from the PWM controller when the clock square wave signal has an ununiform frequency thereby. |
