发明名称 FIELD-EFFECT TRANSISTOR AND FORMATION OF GATE ELECTRODE
摘要 PROBLEM TO BE SOLVED: To provide a high-yield gate structure and a manufacturing method thereof which improves the controllability of a gate length shorter than a mask opening pattern, while suppressing the increase of the leak current of the gate electrode and gate capacitance, and provide a field-effect transistor having superior characteristics at a high frequency range over 10GHz. SOLUTION: An n-AlGaAs carrier feed layer 105 (Al compsn. 0.22, 20nm thick, Si doping concn. 1×10<18> /cm<-3> ), AlGaAs Schottky layer 106 (Al the same compsn., 10nm thick) and GaAs cap layer 107 (140nm thick) are formed, V- groove is etched into the cap layer and part of the Schottky layer 106 (to expose the (111) plane, cap layer surface opening width 250nm), a Schottky gate electrode 108 (of Si) is formed in the groove, and source and drain electrodes 108, 109 (of AuGe/Ni/Au) are formed.
申请公布号 JPH10209177(A) 申请公布日期 1998.08.07
申请号 JP19970010388 申请日期 1997.01.23
申请人 NEC CORP 发明人 NAKAYAMA TATSUPOU
分类号 H01L29/812;H01L21/338;(IPC1-7):H01L21/338 主分类号 H01L29/812
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