Scanning and holding circuit with storage capacitor

摘要

The circuit has a capacitor (C2) with terminal receiving preset potential, and an operational amplifier (OP3) with output and inverting input terminal. The latter is coupled to the other terminal of the storage capacitor. The amplifier has a non-inverting input terminal, to which is applied an input signal. The amplifier contains a phase compensating capacitor and a push-pull circuit with NPN and PNP output transistors, the latter for charging the storage capacitor in response to the input signal. There is an output release circuit for separating the NPN and PNP transistors and for determining the potential in the phase compensation capacitor as a response to a holding signal (S/H).