Phasenregelkreis mit einem Spannungs-gesteuerten Oszillator mit Mehrfrequenzausgang

摘要

A phase locked loop includes a comparator 50, Fig 3 and a VCO 54 having a multi-stage oscillator 68, Fig 4 and a combinational logic stage 70. The comparator is responsive to an input clock 56 and a VCO comparison clock 62 and produces an output 60 to control the VCO 54. The multi-stage oscillator 68 oscillates at a VCO clock frequency during a steady state and provides a plurality of clock phases at the VCO clock frequency. The combinational logic stage 70 is responsive to at least some of the clock phases and combines the clock phases to provide an output clock frequency that is a multiple of the input clock frequency. A frequency divider 63 may be provided. A further aspect relates to the VCO and a method for multiplying an input clock frequency including applying an input clock to a delay chain, developing a plurality of phase shifted clocks by tapping into the delay chain, and combining the plurality of phase shifted clocks in combinational logic stage 70 to produce an output clock having a frequency that is a multiple of the input clock frequency. Examples of the multi-stage oscillator 68 are described (Figs 5, 8, 12, 15a and 15b). Also the combinational logic stage 70 is described in detail (Figs 6a, 6b, 9a-9e, 12 and 13).