| 摘要 |
<p>A signal processor which can be configured to perform interpolation or decimation of an analog input signal, using a combination of continuous-valued discrete-time sampling together with digital filter coefficients. In its preferred embodiment, the signal processor includes a signal sampling circuit configured to produce a continuous-valued discrete-time sequence of the most recent N input samples, with the sequence being stored in a circular buffer arrangement of sample-and-hold circuits. Further, in its preferred embodiment, the signal processor includes a filter coefficient shift-register that stores digital filter coefficients, with the shift register contents being cyclically shifted to maintain the correct time correspondance with the input samples held in the circular buffer of input samples. Further, in its preferred embodiment, connections from the digital filter coefficient shift-register are made to a set of analog-digital multipliers such that polyphase filter coefficients can be extracted from the shift register. The analog-digital multipliers can be of a type that operate as digitally programmable amplifiers, or equivalently, that operate as multiplying digital-to-analog converters. For implementing interpolation by a factor of L (or decimation by a factor of M) the output rate is L times (or 1/M times) the input rate sample, there are L (or M) polyphase filters, the number of polyphase filter outputs that are summed is set to one (or M), and the number of multipliers is equal to N (or N/M). As well, for decimation, an input-phase-selection circuit is employed to provide M polyphase subsequences from the circular buffer of input samples.</p> |
