| 摘要 |
A computer system and method for performing data transfers during idle PCI clock cycles. The computer system includes a PCI bus, a plurality of devices coupled to the bus, and a bus arbiter coupled to the bus. One of the plurality of devices is a source device, such as a CD-ROM drive controller, and one of the plurality of devices is a destination device, such as an MPEG video decoder. The system further includes a source ready signal, a destination ready signal and an idle acknowledge signal each coupled to the bus arbiter, the source device and the destination device. The source device asserts the source ready signal when the source device is ready to send data to the destination device. The destination device asserts the destination ready signal when the destination device is ready to receive data from the source device. The bus arbiter asserts the idle acknowledge signal when each of the plurality of bus request signal and bus grant signal pairs is deasserted and the bus is idle. The source device sends data to the destination device on the next clock after each of the source ready, destination ready and idle acknowledge signals are asserted.
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