发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT DESIGN METHOD THEREFOR
摘要 <p>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit wherein useless power consumption is reduced and clock skew is restrained. SOLUTION: This semiconductor integrated circuit has a clock supply path 20, which has a tree structure and distributes clocks CK to a plurality of flip- flops 11-13. A clock control cell CC, which supplies clocks to the respective branch points according to a control signal, is interposed in one or two or more branch points in the clock supply path 20 of the tree structure. To each of the flip-flops 11-13, a control circuit 30 supplies control signals S1, S2S to the clock control cell CC such that the clock CK is supplied to the flip-flop, only when the flip-flop needs the clock CK.</p>
申请公布号 JPH10199985(A) 申请公布日期 1998.07.31
申请号 JP19970002436 申请日期 1997.01.09
申请人 YAMAHA CORP 发明人 YOKOYAMA MOTOO
分类号 H01L21/822;G06F1/10;G06F17/50;H01L21/82;H01L27/04;(IPC1-7):H01L21/82 主分类号 H01L21/822
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