| 摘要 |
<p>PROBLEM TO BE SOLVED: To increase storage capacity per unit area without increasing the cell area, by arranging a plurality of ferroelectric capacitors wherein a selection transistor is made common, in a memory cell, storing data and controlling the storage data to be read, with a control circuit. SOLUTION: Two ferroelectric capacitors C0 , C1 are connected in parallel with one side impurity diffusion region of a common selection transistor from the storage node electrode 3 side, thereby constituting a memory cell. Memory cells having similar constitutions are regularly arranged on the respective points of intersection of bit lines BL and word lines WL, thereby constituting a memory array whole body. A plate line selecting circuit 5 is arranged in the periphery of the memory array. The word lines WL, two plate lines PL0 , PL1 and a plate voltage supplying line PL are connected with the plate line selecting circuit 5. Thereby, storage capacity per unit area can be improved without increasing cell area.</p> |
