发明名称 COMPOSITE MODE TYPE SUBSTRATE VOLTAGE GENERATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce a leak amount of current at a sub threshold area of a transistor by making a substrate voltage impressed to the transistor at a self refresh operation of a cell consisting of one transistor and one capacitor lower than that impressed at a refresh operation. SOLUTION: A back bias voltage generator 10 generates a first or second back bias voltage in response to a refresh mode control signal NORM or a self refresh mode control signal SREF and supplies to a DRAM. A first, a second back bias voltage detectors 21, 31 compare the first, second back bias voltages with a first, a second reference voltages set thereinside, and send out an enable signal to the back bias voltage generator 10, thereby holding the back bias voltage at a predetermined value. The second reference voltage is set to be 0.5-0.3 times the first reference voltage. Accordingly, a refresh time cycle is relatively elongated.
申请公布号 JPH10199244(A) 申请公布日期 1998.07.31
申请号 JP19970307402 申请日期 1997.11.10
申请人 HYUNDAI ELECTRON IND CO LTD 发明人 SAI SHUZEN
分类号 G11C11/407;G05F3/20;G11C5/14;G11C11/401;G11C11/403;G11C11/4074;G11C11/408;H01L21/8242;H01L27/108 主分类号 G11C11/407
代理机构 代理人
主权项
地址