Multiple parallel identical finite state machines which share combinatorial logic

摘要

N separate identical finite state machines service N corresponding channels. In one embodiment, each channel operating at a clock frequency F is serviced by the same combinatorial logic block which runs at an N*F clock frequency. The channel inputs are delivered to the shared combinatorial logic block via an N-to-1 multiplexor. N separate output registers continuously provide output to the N separate channels. Each output register is loaded every Nth clock cycle. Although the combinatorial logic is shared amongst multiple machines, the state variables for each machine must be stored in a memory unit. In an embodiment of the memory unit, N separate state variable registers are loaded using the same load enable control signals as are used for the N output registers. The current state for the appropriate channel is selected by means of an N-to-1 multiplexor. An N-element shift register sequentially provides the appropriate channel's state variables to the shared combinatorial logic block. In the preferred embodiment of the memory unit, a dual-ported Random Access Memory (RAM) is used to efficiently aggregate the N channels' state variables. One port is dedicated to writing the next state while another port is dedicated to reading the current state. A read/write pointer is implemented as a counter which sequential counts from 0 to N-1 such that the dual-ported RAM behaves identically to a shift register. In another embodiment, the shared combinatorial logic is pipelined into as many as N separate combinatorial equals the number of channels N.