| 摘要 |
PCT No. PCT/FR95/00317 Sec. 371 Date Sep. 16, 1996 Sec. 102(e) Date Sep. 16, 1996 PCT Filed Mar. 16, 1995 PCT Pub. No. WO95/25329 PCT Pub. Date Sep. 21, 1995A fast differential sample-and-hold circuit includes two transistors controlled so as to be turned on or off. The output signal of the circuit is recovered at the terminals of an output capacitor connecting the emitters of the two transistors. The sample-and-hold circuit includes additional circuitry having two dynamic current generators and an additional capacitor which make the current flowing through the transistors constant when they are on. To this end, the two dynamic current generators are modulated by differential current which is output by the additional capacitor and the variations in which reproduce the current variations which appear in the output capacitor.
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