| 摘要 |
A semiconductor memory device is operable in an operation mode selected from a read mode, a normal write mode and a block write mode. The memory device includes a memory cell array having a plurality of pairs of bit lines, a plurality of word lines and a plurality of memory cells provided at intersections of the bit lines and the word lines, wherein each pair of the bit lines and the memory cells associated with each bit line pair form one of a plurality of columns defined in the memory cell array. The memory device also includes a pair of data lines and a column selection controller, wherein the column selection controller is supplied with a group of column selection signals for selectively connecting and disconnecting the pair of data lines to and from the plurality of pairs of bit lines. In response to the group of column selection signals with a first signal output pattern for use in the normal write mode or the read mode, the column selection controller selects one of the plurality of columns to connect the pair of data lines to a pair of bit lines associated with the select column. Further, in response to the group of column selection signals with a second signal output pattern for use in the block write mode, the column selection controller selects at least two of the plurality of columns to connect the pair of data lines to the bit line pairs associated with a column block as a group of the selected columns.
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