发明名称 |
Enhanced dynamic programming method for technology mapping of combinational logic circuits |
摘要 |
A circuit optimization method in which a set of cost functions are stored for each node that indicate the cost of getting signals to that node and the cost of a gate at that node. By "cost", is meant some figure of merit, such as: the maximal delay for a signal to arrive at a node G; or the area of the elements needed to produce the signal at node G. These cost functions enable the circuit to be optimized without the need for a pattern library and the pattern matching process that is typical of other optimization processes, such as the DAGON Node Tiling Procedure.
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申请公布号 |
US5787010(A) |
申请公布日期 |
1998.07.28 |
申请号 |
US19970870860 |
申请日期 |
1997.06.06 |
申请人 |
SCHAEFER, THOMAS J.;SHUR, ROBERT D. |
发明人 |
SCHAEFER, THOMAS J.;SHUR, ROBERT D. |
分类号 |
G06F17/50;(IPC1-7):G06F15/00 |
主分类号 |
G06F17/50 |
代理机构 |
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主权项 |
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地址 |
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