| 摘要 |
A plurality of JFETs (junction field-effect transistors) can be formed on the same substrate while being electrically separated from each other, and can be also combined with a CMOS (complementary metal-oxide semiconductor). A P-type Si layer 14 is fabricated on a semiconductor substrate 11 as an island. On this island of P-type Si layer, an N+ source region 19 and N+ drain region, and a channel region having a length of "Lg" and a channel depth of "Tg" are fabricated. The shape of the gate region with the gate length of "Lg" is not a V-shaped-structure. Another P type layer 21 of the gate region is fabricated on the same plane as the source region 19 and the drain region 15.
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