| 摘要 |
The data signals retained in the data latch circuit are captured securely in the line latch circuit. The data latch control circuit sequentially creates data latch control signals DLC having timing values shifted from one another by one period of a data latch clock signal DLCK. The first n-bit display data DA is retained in the D latch circuits at the first stage of the data latch circuit in accordance with the first signal DLC and then retained in the D latch circuits at the second stage in accordance with the second signal DLC. Furthermore, the second display data DA is retained in the D latch circuits of the data latch circuit. The display data DA for one scanning electrode is retained in the line latch circuit by a capture signal LPS delivered between the termination of the delivery of a horizontal synchronizing signal LP and the termination of the delivery of the first signal DLCK to the next scanning electrode.
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