| 摘要 |
A data transmission system provides outputs having order of bit strings consistent with input bit strings input to an encoder even when erroneous bit strings are output due to frequency division ambiguity. Encoders are arranged in parallel at a transmission side. The arrangement of encoded bit strings input to a parallel/serial converter and respective decoded bit strings input to Viterbi decoder, is made an arrangement disabling error correcting decoding of any one of the decoded for disabling error correction decoding when erroneous bit string is output due to frequency phase ambiguity. The system includes a phase shifter for causing shifting of decoded bit strings to make the decoded bit strings consistent with the arrangement of input bits of the encoder, when error correction decoding is disabled. Also, when four phase ambiguity is caused, the arrangement of the output bit string of the Viterbi decoder is corresponding to the input bit strings of the encoder by a selector. By such constructions, outputs of the order of bit strings can be consistent with those input to encoders, even when bit strings are output in erroneous order due to frequency division phase ambiguity in serial/parallel converters.
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