| 摘要 |
A digital signal processor includes first and second counters which increment from each initial address value in first and second address areas synchronous with first and second sampling clock signals, an address generating circuit which generates a first address number in the above first address area according to a counter value in the above first counter and generates a second address number in the above second address area according to a counter value in the above second counter, a data memory which stores information signals supplied synchronous with the above first and second sampling clock signals in the first and second address numbers generated by the above address generating circuit readably and an arithmetic operating circuit which performs arithmetic operation of information signals stored in the above data memory.
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