发明名称 ATM SWITCH WITH VC PRIORITY BUFFERS
摘要 An ATM network switch comprises a plurality of slot controllers, each having at least one external data link 3, 4 thereto, cell receiving means for receiving ATM cells from the data link and cell transmitting means for transmitting ATM cells outwardly on the data link, each slot controller being connected to a switch fabric comprising means for switching a cell input from one slot controller to a selected one of the other slot controllers for transmission on the external data link connected thereto, wherein each slot controller comprises cell buffering means 23 associated with the cell receiving means and/or the cell transmitting means, the cell buffering means comprising a FIFO 24 for each VC established on the switch, means 22 for determining the VCI for each new cell entering the buffering means and for storing the cell in the appropriate FIFO, and control means for outputting the cells sequentially from each FIFO in turn, the control means comprising an output arbitration FIFO 25, means for sequentially storing in the arbitration FIFO pointers indicating those VC FIFOs containing cells, and output means for reading the pointers and for causing a cell to be output from a respective VC FIFO according to the pointer read.
申请公布号 EP0853851(A1) 申请公布日期 1998.07.22
申请号 EP19960933990 申请日期 1996.10.02
申请人 GENERAL DATACOMM, INC. 发明人 JONES, TREVOR
分类号 H04L12/70;H04L12/931;H04L12/933;H04L12/935;H04L12/939;(IPC1-7):H04L12/56 主分类号 H04L12/70
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