发明名称 A method for optimizing integrated circuit fabrication
摘要 <p>A (20, 60) for optimizing chip size/aspect ratio and reticule layout. The method includes the steps of first generating an initial rectangular shot map (22, 62) having a number of rows and columns of shots, determining which chips in the initial rectangular shot map are geometrically positioned on acceptable areas of a wafer, determining which chips in the initial rectangular shot map are geometrically positioned on low and high yield locations of the wafer, and deleting the empty shots from the initial rectangular shot map for obtaining a temporary best shot map. Thereafter, iteratively shifting the initial rectangular shot map along a first axis until a first predetermined limit is reached, comparing each resultant shifted shot map with the temporary best shot map, and setting the shifted shot map as the temporary best shot map in response to a favorable comparison. After the first predetermined limit is reached, iteratively shifting the initial shot map along a second axis until a second predetermined limit is reached, comparing each resultant shifted rectangular shot map with the temporary best shot map, and setting the shifted shot map as the temporary best shot map in response to a favorable comparison. A best shot map (100, 110) is then generated for wafer fabrication. The chip size is also optimized by a companion method.</p>
申请公布号 EP0854430(A2) 申请公布日期 1998.07.22
申请号 EP19980830002 申请日期 1998.01.08
申请人 TEXAS INSTRUMENTS INCORPORATED;CONSORZIO EAGLE 发明人 SERAPIGLIA, ANTONIO;FACCHINI, ANGELO
分类号 H01L21/66;(IPC1-7):G06F17/50 主分类号 H01L21/66
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