LAYOUT STRUCTURE FOR BARREL SHIFTER WITH DECODE CIRCUIT

摘要

PROBLEM TO BE SOLVED: To accelerate the bit shift processing of data due to a barrel shifter by decreasing the wiring load of bit shift amount data of barrel shifter. SOLUTION: Two flip-flops FFB1 and FFB0, to which bit shift amount data B(1) and B(0) of two bits are inputted, and decode circuits DEC0 and DEC1 for decoding the bit shift amount data from these flip-flops are laid out while being parallelly arranged in one lateral line. These flip-flops and decode circuits are symmetrically laid out for the unit of a bit together with four flip-flops FFA4-FFA0 for inputting data A(4)-A(0) to be bit-shifted of four bits and a bit shifter 2 for shifting the bits of data A(4)-A(0) from these flip-flops just for the bit shift amount decoded by the decode circuits DEC0 and DEC1 and arranged in a data path while taking bit slice structure.