| 摘要 |
PROBLEM TO BE SOLVED: To simplify a circuit for a conversion processing and to reduce a circuit scale by using a transmission pulse generation circuit and outputting the respective signals of parallel data stored in a transmission buffer in a prescribed cycle and in a prescribed time width. SOLUTION: The transmission buffer 1 receives the parallel data DP of 8 bits outputted from a computer or the like and holds them at the timing of inputting buffer write signals BFWRP. Then, the signals of the 8 bits are parallelly outputted to a transmission data synthesis circuit 3. To the respective AND gates 4-1-4-8 of the transmission data synthesis circuit 3, the parallel data outputted by the transmission buffer 1 are respectively inputted by one bit each. In this case, the respective gates 4-1-4-8 open the gates in a fixed order in a fixed cycle set in the transmission pulse generation circuit 2 and output the respective signals of the parallel data stored in the transmission buffer 1 in the prescribed time width to an OR gate 5 by one bit each. |
