SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To keep uniformity in time for access to a memory address to be accessed, to let an on-chip DRAM contribute to accelerate the speed of access to an off-chip DRAM, and further to use a mass memory as a built-in memory. SOLUTION: The hierarchical structure of memory is formed from a CPU (CPU core), primary cache (CAA1 and CDA1) and memory device (on-chip DRAM1). Then, this memory device (DRAM1) enables operation in the state of using two of 1st mode for mapping at a fixed address stored as the main memory of CPU (without extending any external memory) and 2nd mode for operating as the secondary cache of CPU (when extending the external memory).