发明名称 CMOS LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prevent logic errors by the influence of an adjacent circuit by cross-connecting the substrate electrode of an NMOS transistor for forming a function circuit to the output node of the other function circuit in a 2N-2P circuit by an adiabatic charging method constituted of the clamp circuit of a PMOS transistor pair and the function circuit of an NMOS transistor pair. SOLUTION: A power supply line 11 is connected to a pulse power supplyϕand this CMOS logic circuit LOG is operated by the adiabatic charging method. When input IN is at a high level, when the pulse power supplyϕbecomes the high level, the NMOS transistor MN1 of the function circuit FUN1 is conducted and the output /OUT of the output node H02 becomes a low level. Accompanying it, the PMOS transistor MP2 of the clamp circuit CLP is conducted and the output OUT of the output node HO1 becomes the high level. The NMOS transistor MN1 is normally ON since the substrate electrode BN1 is connected to the output node HO1.
申请公布号 JPH10190442(A) 申请公布日期 1998.07.21
申请号 JP19960346028 申请日期 1996.12.25
申请人 SHARP CORP 发明人 KIOI KAZUMASA
分类号 H03K19/0185;H01L27/092;H03K19/00;H03K19/0948;H03K19/096;(IPC1-7):H03K19/094;H03K19/018 主分类号 H03K19/0185
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