| 摘要 |
<p>PROBLEM TO BE SOLVED: To enable a high-speed reading, by dividing a memory cell array into a plurality of sub arrays by a plurality of section decoders having a predetermined distance to a column decoder, and shortening the word line and bit line. SOLUTION: Two units of column decoders 36 and page buffers 35 are arranged between two mats, and a memory cell sub array held between a plurality of section decoders 32 and 33 is arranged between a write decoder 31 and a read decoder 34. Each sub array region has a plurality of pairs of bit lines expanding along corresponding columns, a common source line expanding along at least one corresponding row, and a plurality of word lines and is alternately connected to the section decoders of an odd number and an even number at both sides thereof. A cell unit having a first, a second, a third selection transistors reads with the same timing as a DRAM and erases/writes an EEPROM.</p> |
