ERROR DETECTION METHOD FOR DIFFERENTIAL MODULATION TRANSMISSION SYSTEM, PARITY INSERTION CIRCUIT AND PARITY CHECK CIRCUIT,申请号JP19960343288-传众专利搜索

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发明名称	ERROR DETECTION METHOD FOR DIFFERENTIAL MODULATION TRANSMISSION SYSTEM, PARITY INSERTION CIRCUIT AND PARITY CHECK CIRCUIT
摘要
申请公布号	JPH10190630(A)	申请公布日期	1998.07.21
申请号	JP19960343288	申请日期	1996.12.24
申请人	OKI ELECTRIC IND CO LTD	发明人	AMANO SHIGERU
分类号	H04L27/18;H04L1/00;(IPC1-7):H04L1/00	主分类号	H04L27/18
代理机构		代理人
主权项
地址

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