发明名称 Method for estimating routability and congestion in a cell placement fo integrated circuit chip
摘要 A cell placement for a microelectronic integrated circuit includes a plurality of cells interconnected by nets of wiring. A method for estimating routing density in the placement includes superimposing a pattern of contiguous tiles over the placement, with each of the tiles having edges. Bounding boxes are constructed around the nets, and net probable densities are calculated within each bounding box for the wiring required by each net for each edge respectively. The net probable densities are summed to produce total probable densities of wiring required by all of the nets for each edge respectively. The net probable density for each edge is calculated as being equal to a wiring capacity of the edge divided by the sum of the wiring capacity of the edge and all other unobscured edges within the bounding box that are collinear with the edge respectively. A congestion map can be constructed from the total probable densities and the capacities of the edges, and/or these calculations can be used to predict the routability or unroutability of the placement. Provisions are made for edges that are obscured by large megacells or other obstacles, including providing routing detours around the obstacles.
申请公布号 US5784289(A) 申请公布日期 1998.07.21
申请号 US19960774281 申请日期 1996.12.20
申请人 LSI LOGIC CORPORATION 发明人 WANG, DEBORAH CHAO
分类号 G06F17/50;(IPC1-7):G06F17/10 主分类号 G06F17/50
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