发明名称 SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To avert the substrate floating effect for an n-type MISFET and a p-type MISFET by constituting a region acting as a recombination center for a hole, so as to be in contact with a source-bottom surface junction. SOLUTION: A gate protecting insulation film 7 and a gate electrode 6 are used as an implantation blocking mask. The ion implantation of As is performed. Thereafter, heat treatment is performed, and an n-type high- concentration source diffusing layer 91 and an n-type high-concentration drain diffusing layer 101 are formed. Then, the vertical ion implantation of Ar is performed through an opening, formed in a wiring protecting insulation layer 13 so that the concentration becomes maximum at the interface of an insulating film under the n-type high-concentration source diffusing layer 91 and the n-type high-concentration drain diffusing layer 101. Thereafter, heat treatment is performed. Thus, a p-type crystal defect region 11 comprising minute particle diameter polycrystals is formed in the vicinity of the interface of the insulating film. In the MISFET, various characteristics attributed to the substrate floating effect are completely dissolved.
申请公布号 JPH10189959(A) 申请公布日期 1998.07.21
申请号 JP19960349413 申请日期 1996.12.27
申请人 HITACHI LTD 发明人 HORIUCHI KATSUTADA
分类号 G11C11/401;H01L21/8238;H01L21/8242;H01L21/8244;H01L27/092;H01L27/108;H01L27/11;H01L29/78;H01L29/786;H03K19/0944;H03K19/20 主分类号 G11C11/401
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