发明名称 |
Fault detection in digital system |
摘要 |
For fault testing in a digital system, a processor unit is made available from other activities and the logical units to be tested are set to a predetermined state. An output response analyze is activated and the processor unit generates a set of stimuli, influencing the appropriate logical units. The output response analyzer collects responses to the stimuli at different nodes in the digital system and creates signatures from them. The signals are verified and if a fault is noticed, this error is noticed. The present state of the processor and other logical units are stored in a storage device prior to the test and recovered after the testing is finished. This fault testing can be performed both at chip and board levels, and on systems with several units. |
申请公布号 |
SE9802559(D0) |
申请公布日期 |
1998.07.16 |
申请号 |
SE19980002559 |
申请日期 |
1998.07.16 |
申请人 |
TELEFONAKTIEBOLAGET LM ERICSSON |
发明人 |
PER ANDERS *HOLMBERG;DAN OLOV *HALVARSSON;LARS TOMAS *JONSSON |
分类号 |
G06F11/277;(IPC1-7):G06F/ |
主分类号 |
G06F11/277 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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