发明名称 Modulo address generator circuit for digital signal processing
摘要 The modulo address generator is used in a digital signal processor to enhance the execution of algorithms. The generator has a first adder 21 that adds an increment to the actual address. A second adder 22 generates the complement of the maximum address to a minimum address to provide a cycle correction value. An adder/ subtractor 23 generates a corrected address that is fed to a multiplexer 25 controlled by a comparator 24
申请公布号 DE19748547(A1) 申请公布日期 1998.07.16
申请号 DE19971048547 申请日期 1997.11.03
申请人 SAMSUNG ELECTRONICS CO. LTD., SUWEON, KYUNGKI, KR 发明人 RIM, MIN-JOONG, YONGIN, KYUNGKI, KR
分类号 G06F15/78;G06F5/10;G06F7/72;G06F9/355;(IPC1-7):G06F12/02 主分类号 G06F15/78
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