| 摘要 |
A trigger signal generating circuit comprises a counter for counting up input clock pulses and outputting a trigger signal when the counter counts up to a predetermined number of clock pulses, a CPU for outputting a mask request of a first trigger signal, a first flip-flop for storing the mask reques t of the CPU, a second flip-flop for latching a normal output signal of the first fli p-flop by the trigger signal of the counter, and an AND circuit for calculating a logical sum of a mask request signal output from the second flip-flop and the trigger output from the counter so as to mask the first trigger signal output from the counter or so as not to output a superfluous trigger signal when a timing of a trigger signal generation is delayed.
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