Dual-differential-pair emitter-coupled logic complementary-output circuit

摘要

A complementary-output vertically-stacked ECL gate circuit is disclosed which is low in power dissipation and fast in operation. The ECL gate circuit has a dual differential pair circuit arrangement provided with a pair of complementary outputs and an active pull-down circuit at each of the outputs. This arrangement allows complementary currents to flow through current switching circuits for the respective differential pair circuits and thus provides complementary outputs with built-in active pull-down circuits.