发明名称 A METHOD FOR SCHEDULE VALIDATION OF EMBEDDED SYSTEMS
摘要 Efficient methods for verifying the timing behavior of a system in which various tasks are executed on a processor, and each task is enabled (i.e., becomes ready to execute) in response to the occurrence of an external event and/or the completion of another task. The methods are computationally efficient, requiring an execution time that is polynomial in the number of tasks in the system. The methods can be used in complementary fashion with more computationally intensive techniques for timing behavior verification, such as simulation or prototyping, by limiting the use of such techniques to those systems whose correctness is not proven by the methods.
申请公布号 WO9829808(A1) 申请公布日期 1998.07.09
申请号 WO1997US24131 申请日期 1997.12.30
申请人 CADENCE DESIGN SYSTEMS, INC.;BALARIN, FELICE 发明人 BALARIN, FELICE
分类号 G06F9/48;(IPC1-7):G06F9/46 主分类号 G06F9/48
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