发明名称
摘要 PURPOSE:To reduce the size of a memory cell by forming first and second connection conductors at the place lower than the surfaces of first and second semiconductor regions. CONSTITUTION:The bases and collectors of first and second npn (or pnp) transistors (Tr) Q3 and Q4 are cross-connected with each other, thereby constituting a flip-flop circuit. A first semiconductor layer of a first conductivity type of the first Tr Q3 and a second semiconductor layer of a second conductively type of the second Tr Q4 are connected to each other through a conductor provided under the semiconductor. Similarly, a first semiconductor layer of the first conductivity type of the second Tr Q4 and a second semiconductor layer of the second conductivity type of the first Tr Q3 are connected with each other through the conductor.
申请公布号 JP2773259(B2) 申请公布日期 1998.07.09
申请号 JP19890169069 申请日期 1989.06.30
申请人 发明人
分类号 H01L27/082;H01L21/8222;H01L21/8229;H01L27/102 主分类号 H01L27/082
代理机构 代理人
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