发明名称 |
Method and apparatus for disabling interrupts in a highly pipelined processor |
摘要 |
A method and apparatus disables and re-enables an interrupt during the execution of certain I/O and memory operations in an out-of-order processor. The out-of-order processor executes macroinstructions, wherein each macroinstruction comprises one or more microinstructions. The out-of-order processor comprises a fetch and issue unit and a reorder buffer that allows an interrupt to be serviced during the execution of the microinstructions making up any of a first class of macroinstructions. The reorder buffer, however, does not allow the interrupt to be serviced during execution of microinstructions making up a second class of macroinstructions. The second class of macroinstructions may include I/O and memory operations.
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申请公布号 |
US5778220(A) |
申请公布日期 |
1998.07.07 |
申请号 |
US19960749896 |
申请日期 |
1996.11.18 |
申请人 |
INTEL CORPORATION |
发明人 |
ABRAMSON, JEFFREY M.;KONIGSFELD, KRIS G.;VIDWANS, ROHIT A. |
分类号 |
G06F9/38;G06F11/00;(IPC1-7):G06F9/22 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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