| 摘要 |
A method for performing a hierarchial timing driven layout of a circuit based upon gate-level design data and circuit timing constraints, the circuit including a plurality of cells, includes: partitioning the plurality of cells into a plurality of logical blocks, a first logical block including a first plurality of cells; budgeting a block timing constraint for each of the plurality of logical blocks in response to the gate-level design data, to the circuit timing constraints, and to the partitioning of the plurality of cells into the plurality of logical blocks; placing the plurality of logical blocks within a circuit floorplan, each logical block associated with a block location within the circuit floorplan; rebudgeting the block timing constraint for at least one of the plurality of logical blocks in response to the placement of the plurality of logical blocks within the circuit floorplan; placing the first plurality of cells within a block location associated with the first logical block; and rebudgeting the timing constraint for at least one of the plurality of logical blocks in response to the placement of the first plurality of cells within the first logical block.
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