| 摘要 |
A column select multiplexer for a memory array organized in modules, each module handling two sets or bunches each of a certain minimum number of bitline, is realized in a space opposite to the bitline terminations and the select transistors are realized along an uninterrupted active area strip by realizing isolation gates between adjacent diffusions of two distinct select transistors. The bitlines of the two bunches handled by a multiplexer module are preferably interleaved and the respective select transistors are realized along two parallel uninterrupted active area strips.
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