| 摘要 |
A nonvolatile memory cell (10) includes a single n-channel insulated gate FET (11) having a single floating gate (12). The FET (11) operates asymmetrically in a sense that the capacitance of a parasitic gate-source capacitor (24) is smaller than the capacitance of a parasitic gate-drain capacitor (26). The asymmetric condition is achievable either by fabricating the FET (11) as an asymmetric structure (30, 60) or by adjusting the capacitance of the parasitic capacitors (24, 26) through terminal biasing when the FET (11) is a short channel device. The potential of the floating gate (12) is controlled by biasing the source (14), drain (16), and substrate (18) of the FET (11). The cell (10) is programmed by moving charge onto the floating gate (12) via hot carrier injection, erased by moving charge from the floating gate (12) via tunneling, and read by sensing the conductive state of the FET (11).
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