Matrix processor for image recognition processing

摘要

The processor (1) for matrix calculations has a control unit (2,3) and a data memory (4). It also includes several calculating units (6 - 14) which use the data present in the data memory. The calculating units are controlled by the control unit via a control bus composed of: - a first wire group connected to the calculating units to convey a common instruction (19) to the units. A number of second groups of at least one wire are each respectively connected to one of the calculating units of the units. Each second group conveys a specific complement instruction (20) to each calculating unit of the units. Each calculating unit has at least: - an accumulator (29) of n + k bits having an input and an output of n + k bits. The accumulator memorises a data in the calculating unit; - an arithmetic and logic unit (26) having first and second inputs of n + k bits and an output of n + k bits. The unit can carry out different arithmetic and logic operations.