Verfahren zur Herstellung einer Speicherzellenanordnung

摘要

In order to manufacture a memory cell configuration comprising a first series of memory cells including a vertical MOS transistor and a second series of memory cells without MOS transistor, the memory cells being arranged along the opposing flanks of strip-shaped pits, tiled memory cells are built one after the other along said pits (5). The spacing between the memory cells is determined according to a spacer technology enabling to meet the space need per memory cell, i.e. 1F<2>, where F represents the minimum structural quantity specific to said technology.