| 摘要 |
A data variation detecting system can perform detection of data variation at an arbitrary timing without lowering process performance of a processing unit, and without requiring expansion of a memory region in the processing unit. In the data variation detecting system, a recent data and a preceding data are taken from a shift register, are compared by a comparator circuit for detecting whether data variation is present or not by a data variation detecting circuit. The recent data is stored in a memory of an interface circuit with a data holding circuit. A result of detection by the data variation detecting system is directly stored in the memory in the interface circuit. When data variation is detected, operation of storing the recent data by the shift register and the data holding means is disabled via a masking circuit. The occurrence of data variation is detected by the processing unit via the interface circuit, the processing unit obtains the recent data from the interface circuit. When a reset signal demanding resumption of the data variation detecting process is input to the interface circuit by the processing unit, the interface circuit outputs the reset signal to a re-timing circuit. The re-timing circuit is responsive to the reset signal for resuming data variation detection at a timing of completion of taking of data in a monitoring zone. <IMAGE> |
