ENHANCED METHODS AND SYSTEMS FOR CACHING AND PIPELINING OF GRAPHICS TEXTURE DATA

摘要

Circuits and methods for enhanced caching and pipelining of graphics texture data within a computer controlled graphics display system. The present invention includes: an improved three level texture map memory caching system; a pixel pipeline coupled to the output of a triangle engine for reducing triangle engine stalls, and a tile-in-tile (e.g., tile and subtile) texture map memory management scheme for increasing texture cache hits. These three systems cooperate together to increase graphics throughput within the computer controlled graphics display system. The three level texture map memory caching system includes a first level cache (L1) residing in the texture engine and contains subtiles that are cached in and out on a least recently used (LRU) basis. The second level cache (L2), e.g., in the off-screen RAM, is a larger cache that caches in and out tile length data. The third level cache (L3) resides in the host computer's main memory. In one embodiment, L1 is approximately 2k bytes, L2 is approximately 128k bytes, and main memory is accessible up to 32M bytes. The pixel pipeline coupled to the triangle engine advantageously allows the processing of triangle polygon information (e.g., color) during a texture data fetch interval of the texture engine. Additionally, the tile-in-tile memory addressing system provides a memory management technique that increases the chances of cache memory hits within the texture engine of the present invention by caching specially arraigned tiles and subtiles thereof during texture map data access operations.