Frequency multiplier for controlling pulse width

摘要

The frequency multiplier has an input signal delay circuit (101), and an exclusive-OR gate (102) which combines the delayed and undelayed input signals. There is an inverter (103,104) for the signal from the gate, a low-pass filter (105) for the gate output, together with a comparator (106) for a high voltage, a comparator (107) for a low voltage and inverters (108,109) for the comparator output signals. The comparators compare the signal from the filter with high and low threshold voltages, and output switch control signals. The inverters for the comparator outputs delivers a signal to the delay unit.