发明名称
摘要 PURPOSE:To reset a control system consisting of multi CPU or the like surely and in a short period of time. CONSTITUTION:When a power supply output from power supply 1 for an on/off controllable driving system is turned off by the main CPU 11, the power supply output is forcibly discharged by a lamp 12 and transistor 13, and by a diode 25 the reverse flow of current to the power supply 1 from a load system is protected. Further, when the main CPU 11 detects the drop of the power output by power off is detected by inputting a signal from analog input port AN, the power supply 1 is turned on again, thereby activating reset circuits 16, 17, and 18 of sub CPU 15 to rest the sub CPU 15.
申请公布号 JP2771043(B2) 申请公布日期 1998.07.02
申请号 JP19910037425 申请日期 1991.03.04
申请人 KYANON KK 发明人 KIMIZUKA JUNICHI;SATO KAORU;TACHIBANA TATSUTO;NAKAMORI TOMOHIRO;KYONO JUZO;KUSANO AKIHISA;NARITA IZUMI
分类号 G03G21/00;G03G15/00;G06F1/24 主分类号 G03G21/00
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